Status and Control Signals

XiBIF provides a set of status and control signals that can be read in the FPGA. These signals are integrated in the register map of the Streaming Interface and cannot be accessed with register read and write functions.

Ethernet Status

To detect whether a connection with a Host device is established, the signal SnCHostConnectedxDO can be read. This signal is high when a connection is established and low when no connection is present. It gets updated every time the Host device connects or disconnects. In case of a forceful disconnection (as it can occur due to unplugging the network cable), the signal will be updated after a timeout of 1 second.

Note

The default timeout can be modified in the project file. Additionally, it is possible to define whether the streaming FIFOs are flushed when a connection is dropped. See Configuring Ethernet settings for more information on how to change these values.

Software Reset

To perform a reset of the programmable part of the FPGA, the signal SnCSoftwareResetxRO is provided. This signal can be written via Python and is high for one clock cycle when the reset is asserted.

handleXiBIF.perform_software_reset()

Note

The software reset does not fully reset the FPGA. It only resets the programmable part of the FPGA connected to this signal. The rest of the FPGA, including the Streaming Interface, remains unaffected. By default, this signal is not connected and must be connected by the user.

Streaming FIFO Status

The signals RdFIFOLevelxDO and WrFIFOLevelxDO provide information about the status of the Streaming FIFOs.

• RdFIFOLevelxDO: Indicates the number of words currently in the FIFO (PC->PL stream). The PL can read this many words from the FIFO.

• WrFIFOLevelxDO: Indicates the number of words currently in the FIFO (PL->PC stream). The PL has written already this many words into the FIFO. As soon as the data is transferred to the DDR, the FIFO level decreases.