Quickstart

This quickstart guide provides the essential commands to get you up and running with XiBIF quickly. For detailed information, please refer to the linked sections.

Installation

Create a virtual environment:

python -m venv .venv-xibif

Activate the virtual environment:

.venv-xibif\Scripts\activate  # Windows
source .venv-xibif/bin/activate  # Linux/macOS

Install XiBIF using pip:

pip install XiBIF --index-url https://gitlab.ost.ch/api/v4/groups/12907/-/packages/pypi/simple

Verify the installation:

xibif -v

For detailed installation instructions including prerequisites and virtual environment setup, see Installation.

Creating a New Project

Create a new XiBIF project with:

xibif new -n <project_name> -p <project_path> -b <board> -x <xilinx_path> -v <xilinx_version>

Example:

xibif new -n MyProject -p D:\projects\myproject -b zedboard -x C:\Xilinx -v 2024.2

Quick Reference:

  • -n: Project name

  • -p: Project path

  • -b: Board (e.g., zedboard, …)

  • -x: Xilinx installation path

  • -v: Xilinx version

For more details, see Hardware Design Flow.

Building Your Project

Build the complete project (hardware + software):

xibif build

This command performs synthesis, place-and-route, bitstream generation, and software compilation. The result is a BOOT.bin file in hw/results/ that can be copied to an SD card.

Build Hardware Only:

xibif build --vivado all

Build Software Only:

xibif build --vitis all

Build Specific Stages:

xibif build --vivado synthesize
xibif build --vivado bitstream --vivado export --vitis all

For more information on the build process, see Hardware Design Flow.

Flashing the FPGA

Flash the bitstream to a running FPGA (non-persistent):

xibif flash

For more details, see Hardware Design Flow.

Simulating Your Design

Generate a testbench for your VHDL file:

xibif testbench -f <my_file.vhd> -c <clock_signal> -rn <reset_signal>

Example:

xibif testbench -f adder.vhd -c clk_in -rn resetn_in

This generates testbenches in hw/tb/ and hw/tb/vunit/ with clock and reset generators.

Run all simulations using VUnit:

xibif simulation

Run Specific Test:

xibif simulation -t <test_name>

List Available Tests:

xibif simulation -l

Debug with GUI:

xibif simulation -g

For detailed simulation setup and VUnit usage, see Simulation.

Connecting to Your FPGA

In your Python script:

from xibif import XibifConnection

# Create connection
connection = XibifConnection(ip_address="192.168.1.10", verbose=False)
connection.open()

# Read/write registers
connection.write(address, data)
data = connection.read(address)

# Stream data
connection.write_stream(data_array)
data = connection.read_stream_all()

# Close connection
connection.close()

For network configuration and connection details, see Ethernet Connection and Writing Software.

Working with Registers

Use the generated register map for easy register access:

from regs import RegMap

regs = RegMap(connection)

# Write to register
regs.register_1 = 0x1234

# Write to bitfield
regs.register_1_bf.field_1 = 1

# Read from register
value = regs.register_2

# Read from bitfield
field_value = regs.register_2.field_1

For detailed register usage and generation, see Register Generation and Writing Software.

Opening Xilinx Tools

Open Vivado with your project:

xibif start vivado

Open Vitis with your project:

xibif start vitis

Start the hardware server:

xibif start hardware_server

Getting Help

View all available commands:

xibif --help

View help for a specific command:

xibif build --help
xibif new --help

Next Steps

Now that you know the basics, explore these topics for more in-depth knowledge: