XiBIF Base Classes

class XibifProject(name: str, path)

A serializable class containing XiBIF project information.

The project information can be used to setup custom tooling, folder structures and keep track of project flow.

property board: str

Get the target board name.

Returns:

Board name.

Return type:

str

property compile_vunit_folder: Path

Get the VUnit compilation folder path.

Returns:

Path to the VUnit compilation folder.

Return type:

Path

property compile_xilinx_folder: Path

Get the Xilinx compilation folder path.

Returns:

Path to the Xilinx compilation folder.

Return type:

Path

create_backup() → Path

Create a backup of the whole folder structure of the project.

Returns:

The path to the backup folder.

Return type:

Path

Raises:

FileExistsError – Backup folder already exists.

create_folders(force: bool)

Create all folders for the project.

Parameters:

force (bool) – Should overwrite existing folders?

Raises:

FileExistsError – A file would be overwritten by the action.

property csserver_binary: Path

Get the path to the CS Server executable.

Returns:

Path to the CS Server binary.

Return type:

Path

property custom_reg_checksum: str

Get the custom register file checksum.

Returns:

Checksum of the custom register file.

Return type:

str

property custom_reg_config: str

Get the custom register configuration path.

Returns:

Path to the custom register configuration file.

Return type:

str

property doc_folder: Path

Get the documentation folder path.

Returns:

Path to the documentation folder.

Return type:

Path

property enable_webserver: bool

Get the webserver enable flag status.

Returns:

True if the webserver is enabled, False otherwise.

Return type:

bool

property ethernet_connection_drop_flush_fifo: bool

Get the connection drop FIFO flush flag.

Returns:

True if FIFO should be flushed on connection drop, False otherwise.

Return type:

bool

property ethernet_gateway: str

Get the default Ethernet gateway.

Returns:

Gateway IP address string.

Return type:

str

property ethernet_ip: str

Get the default Ethernet IP address.

Returns:

IP address string.

Return type:

str

property ethernet_mac: str

Get the Ethernet MAC address.

Returns:

MAC address string.

Return type:

str

property ethernet_netmask: str

Get the default Ethernet netmask.

Returns:

Netmask string.

Return type:

str

property ethernet_timeout_connection_drop: int

Get the connection drop timeout in milliseconds.

Returns:

Connection drop timeout in milliseconds.

Return type:

int

property ethernet_timeout_dhcp: int

Get the DHCP timeout in seconds.

Returns:

DHCP timeout in seconds.

Return type:

int

property freeze: bool

Get the freeze flag status.

Returns:

True if the project is frozen, False otherwise.

Return type:

bool

from_config(project_path: Path, hide_checksum_warning: bool = False)

Populate the contents of a XibifProject class from a project configuration file.

Parameters:

• project_path (Path) – The path to the project file.

• hide_checksum_warning (bool) – Hide the checksum warning. Defaults to False.

Raises:

FileNotFoundError – The path to the project file is invalid.

classmethod get_xibif_project_file_name() → str

Get the name of the project file.

Returns:

The name of the project file.

Return type:

str

property hdl_src_folder: Path

Get the HDL source folder path.

Returns:

Path to the HDL source folder.

Return type:

Path

property hdl_tb_folder: Path

Get the HDL testbench folder path.

Returns:

Path to the HDL testbench folder.

Return type:

Path

property hw_folder: Path

Get the hardware folder path.

Returns:

Path to the hardware folder.

Return type:

Path

property hwserver_binary: Path

Get the path to the HW Server executable.

Returns:

Path to the HW Server binary.

Return type:

Path

property matlab_folder: Path

Get the MATLAB folder path.

Returns:

Path to the MATLAB folder.

Return type:

Path

property name: str

Get the project name.

Returns:

Project name.

Return type:

str

nuke_folders()

Remove the whole project folder.

property openlogic_folder: Path

Get the OpenLogic folder path.

Returns:

Path to the OpenLogic folder.

Return type:

Path

property project_path: Path

Get the full path to the project configuration file.

Returns:

Path to the project configuration file.

Return type:

Path

property python_folder: Path

Get the Python folder path.

Returns:

Path to the Python folder.

Return type:

Path

read_config(upgrade: bool = False)

Read a project configuration file.

Parameters:

upgrade (bool) – Allow partial validation for upgrade scenarios. Defaults to False.

Raises:

ValidationError – The configuration file is invalid.

property reg_checksum: str

Get the register file checksum.

Returns:

Checksum of the register file.

Return type:

str

property reg_folder: Path

Get the register definition folder path.

Returns:

Path to the register definition folder.

Return type:

Path

remove_folders(ignore_errors: bool = False)

Remove all folders of the project.

Parameters:

ignore_errors (bool) – Ignore errors when removing folders. Defaults to False.

property results_folder: Path

Get the results folder path.

Returns:

Path to the results folder.

Return type:

Path

property settings64_script: Path

Get the path to the Xilinx settings64 script.

Returns:

Path to the settings64 script.

Return type:

Path

property sigasi_folder: Path

Get the Sigasi project folder path.

Returns:

Path to the Sigasi project folder.

Return type:

Path

property simulation_coverage_folder: Path

Get the simulation coverage folder path.

Returns:

Path to the simulation coverage folder.

Return type:

Path

property simulation_history_folder: Path

Get the simulation history folder path.

Returns:

Path to the simulation history folder.

Return type:

Path

property simulation_xml_file: str

Get the simulation XML results file path.

Returns:

Path to the simulation XML results file.

Return type:

str

property sw_folder: Path

Get the software folder path.

Returns:

Path to the software folder.

Return type:

Path

property timeout_axi_firewall: int

Get the AXI Firewall timeout in clock cycles.

Returns:

AXI Firewall timeout in clock cycles.

Return type:

int

update_config(config_data: dict)

Update the config of the project.

Parameters:

config_data (dict) – The new configuration data.

Raises:

ValidationError – The configuration file is invalid.

property uuid: int

Get the project UUID.

Returns:

Project UUID.

Return type:

int

property vitis_binary: Path

Get the path to the Vitis executable.

Returns:

Path to the Vitis or XSCT binary depending on version.

Return type:

Path

property vitis_folder: Path

Get the Vitis project folder path.

Returns:

Path to the Vitis project folder.

Return type:

Path

property vitis_folder_check_moved: Path

Get the absolute Vitis folder path for move detection.

Returns:

Absolute path to the Vitis folder for checking if it has been moved.

Return type:

Path

property vitis_src_folder: Path

Get the Vitis source folder path.

Returns:

Path to the Vitis source folder.

Return type:

Path

property vivado_binary: Path

Get the path to the Vivado executable.

Returns:

Path to the Vivado binary.

Return type:

Path

property vivado_folder: Path

Get the Vivado project folder path.

Returns:

Path to the Vivado project folder.

Return type:

Path

write_config()

Write a project configuration file.

property xilinx_path: Path

Get the Xilinx installation path.

Returns:

Path to the Xilinx installation directory.

Return type:

Path

property xilinx_version: str

Get the Xilinx tools version.

Returns:

Xilinx version string (e.g., “2024.2”).

Return type:

str

property xsct_binary: Path

Get the path to the XSCT executable.

Returns:

Path to the XSCT binary.

Return type:

Path

class XibifConnection(ip_address: str = '192.168.1.10', verbose: bool = False, uuid: int = None, register_width: int = 32)

A class to interface with a XiBIF board.

The xibif interface allows to easily read, write and stream data from/to an FPGA connected via an ethernet cable. Data transfer takes place via sockets and allows for moderate data rates in the dozens of MBits per second.

class AxiAccessStatus(value)

property bitstreamEnabled: bool

Returns true if the bitstream connection is enabled.

Returns:

True if the bitstream connection is enabled, False otherwise.

Return type:

bool

close() → None

Close the connection to a XiBIF board.

Closes all sockets that are connected to a XiBIF board.

property disable_axi_check_DEC0DEE3_DEADFA11: bool

Returns the status of the AXI check disable flag.

Returns:

True if the AXI check is disabled, False otherwise.

Return type:

bool

echo_test(L: int, N: int) → None

Perform an echo test.

Performs a speed test on the device.

Parameters:

• L (int) – The number of values to send.

• N (int) – The number of times to repeat the test.

property errorPc2Pl: int

Returns the error status from PC to PL.

Returns:

Errorcode from PC to PL. 0 means no error. 1 means AXI-Error, 2 means FIFO overflow. Combinations are possible.

Return type:

int

property errorPl2Pc: int

Returns the error status from PL to PC.

Returns:

Errorcode from PL to PC. 0 means no error. 1 means AXI-Error, 2 means FIFO overflow. Combinations are possible.

Return type:

int

property fifoPc2PlDepth: int

Returns the depth of the FIFO from the PC to the PL.

Returns:

The depth of the FIFO from the PC to the PL.

Return type:

int

property fifoPc2PlFill: int

Returns the fill level of the FIFO from PC to PL.

This method reads the status of the FIFO and returns the fill level, which indicates how many elements are currently stored in the FIFO.

Returns:

The fill level of the FIFO from PC to PL.

Return type:

int

property fifoPl2PcDepth: int

Returns the depth of the FIFO buffer between the PL and PC.

Returns:

The depth of the FIFO buffer.

Return type:

int

property fifoPl2PcFill: int

Retrieves the fill level of the FIFO between the PL and PC.

This method reads the status of the FIFO and returns the fill level, which indicates how many elements are currently stored in the FIFO.

Returns:

The fill level of the FIFO between the PL and PC.

Return type:

int

flush_stream() → None

Flush the hardware FIFOs.

Resets the AXI-Stream by discarding all values in the hardware FIFOs.

property ip_address: str

Returns the IP address of the object.

Returns:

The IP address.

Return type:

str

open(flush: bool = True) → None

Open the connection to a XiBIF board.

Initializes all necessary socket connections. If a connection cannot be established, the function times out.

Parameters:

flush (bool) – If True, the stream is flushed before opening the connection. Defaults to True.

Raises:

Exception – An error occurred while opening a connection or reading the device status.

property pc2PlEnabled: bool

Returns true if the PC to PL stream is enabled.

Returns:

True if the PC to PL stream is enabled, False otherwise.

Return type:

bool

perform_software_reset() → None

Perform a software reset on the XiBIF device.

Resets the XiBIF PL part by performing a software reset. Note: The corresponding reset signal needs to be connected manually. The reset is high for one clock cycle.

Raises:

RuntimeError – The connection is not open.

property pl2PcEnabled: bool

Returns true if the PL to PC stream is enabled.

Returns:

True if the PL to PC stream is enabled, False otherwise.

Return type:

bool

print_status_uart() → None

Print the status of a connected XiBIF device.

Prints the device status to the console.

Raises:

RuntimeError – The connection is not open.

read(addr: int) → int

Read the value of a register.

Reads the value of the given address. If a field in a register has software access type ‘read-only’, zeroes are returned for that field regardless of its content.

Parameters:

addr (int) – The relative address of the register in the register block.

Returns:

The value of the register.

Return type:

int

read_axi(addr: int) → int

Read the value of an AXI register.

Reads the value of the given AXI address. If a field in a register has software access type ‘read-only’, zeroes are returned for that field regardless of its content.

Parameters:

addr (int) – The relative address of the AXI register in the register block.

Returns:

The value of the AXI register.

Return type:

int

Raises:

RuntimeError – Failed to read data from AXI device.

read_registermap() → <module 'json' from '/usr/local/lib/python3.11/json/__init__.py'>

Read the register map from the XiBIF device.

Reads the register map in JSON format from the XiBIF device.

Returns:

The register map in JSON format.

Return type:

json

Raises:

RuntimeError – The connection is not open.

read_status() → None

Read the status of a connected XiBIF device.

Reads the device status from the XiBIF stream registers.

Raises:

• RuntimeError – The connection is not open.

• RuntimeError – Failed to read the device status.

read_stream(length: int) → list[int]

Read a stream of data from the device.

Reads the given number of words (32 bit) from the hardware FIFO. The hardware FIFOs data is produced by an AXI-Stream master.

Parameters:

length (int) – The number of words to read.

Returns:

Data from stream.

Return type:

list(int)

read_stream_all() → list[int]

Read all available data from the stream.

Reads all available data from the hardware FIFO. The hardware FIFOs data is produced by an AXI-Stream master.

Returns:

Data from stream.

Return type:

list(int)

set_debug_uart(enable: bool = False) → None

Set debug output on the XiBIF device.

Enables or disables the debug output on the XiBIF device.

Parameters:

enable (bool) – Enable or disable the debug output. Default is False.

Raises:

RuntimeError – The connection is not open.

property socket_timeout: int

Returns the socket timeout value in seconds.

Returns:

The socket timeout value.

Return type:

int

property verbose: bool

Get the value of the verbose attribute.

The verbos attribute controls the data that is logged to the console.

Returns:

Verbosity

Return type:

bool

property version: str

Returns the version of the Python code.

Returns:

The version of the Python code.

Return type:

str

property versionFW: str

Returns the version of the firmware.

Returns:

The version of the firmware.

Return type:

str

property versionHWReg: str

Returns the version of the hardware user registers.

Returns:

The version of the hardware user registers.

Return type:

str

property versionHWStream: str

Returns the version of the hardware stream registers.

Returns:

The version of the hardware stream registers.

Return type:

str

write(addr: int, data: int) → None

Set the value of a register.

Writes the given value to the given address. The data is sent on the register socket and is mapped to the correct AXI address on the device.

Parameters:

• addr (int) – The relative adress of the register in the register block.

• data (int) – The data to write

write_axi(addr: int, data: int, mask: int = 4294967295) → None

Write data to an AXI address.

Writes the given data to the specified AXI address. The data is sent on the register socket and is mapped to the correct AXI address on the device.

Parameters:

• addr (int) – The relative address of the AXI register in the register block.

• data (int) – The data to write.

• mask (int, optional) – The mask to apply during the write operation. Defaults to 0xFFFFFFFF.

Raises:

RuntimeError – Failed to write data to AXI device.

write_bitstream(path: str, addressStream: int = 1136656384, addressRegs: int = 1137704960) → None

Write a bitstream to the XiBIF device.

The bitstream is sent to the device and written to the PL part of the FPGA.

Parameters:

• path (Path) – The path to the bitstream file.

• addressStream (int, optional) – The address where the XiBIF stream peripheral has on the AXI interface, defaults to 0x43C00000

• addressRegs (int, optional) – The address where the XiBIF register peripheral has on the AXI interface, defaults to 0x43D00000

Raises:

• RuntimeError – The connection is not open.

• RuntimeError – The bitstream file does not exist.

write_stream(data: list[int]) → None

Write a stream of data to the device.

Writes the given stream to the device where it will be written to the hardware FIFO. The data can then be sinked by an AXI-Stream slave.

Parameters:

data (list(int)) – Data to stream

class XibifShell(connect_board: bool, load_reg_file: bool, ip)

do_format(args)

Change the displayed number format

do_load(args)

Load a register file

do_open(args)

Open a connection to board

do_reg(args)

Perform register reads and writes

do_repeat(args)

Repeat a command a number of times

do_status(args)

Print the status of the connected board

do_stream(args)

Read/write the AXI-Stream

do_test(args)

Perform a speedtest of the stream connection

get_read_value(input_value: int) → str

Converts the input integer to a string representation based on the current read format.

Args:

input_value (int): The integer value to be converted.

Returns:

str: The string representation of the input based on READ_FORMAT.

Raises:

ValueError: If the READ_FORMAT is invalid.

get_write_value(input_value: str) → int

Converts the input string to an integer based on the current write format.

Args:

input_value (str): The input string representing the value.

Returns:

int: The integer representation of the input based on WRITE_FORMAT.

Raises:

ValueError: If the WRITE_FORMAT is invalid or the input cannot be converted.

load_registers(regpath)

Dynamically loads the register file and retrieves its contents.