Introduction

XiBIF, short for Xilinx Board Interface, is both a hardware platform and a Python package to help you design your FPGA projects. It aims to reduce the barrier of entry for hardware design by simplifying the processes of interfacing with the FPGA from a host computer.

Using the XiBIF hardware platform in your project lets you start with hardware design right away and removes the rather daunting task of having to interface the SoC’s programmable logic (PL) with the processing system (PS) and then also having to install an operating system to communicate over IP, write drivers, test them, and…

You see where this is going; XiBIF abstracts those complications away and does not get in your way when you proceed to implement the communication yourself.

Block Diagram

Block Diagram of an FPGA System with XiBIF

Features

The highlight features of XiBIF are:

  • Connect to an FPGA board over Ethernet.

  • Register generation from a configuration file.

  • Many register modes, such as read-only, write-only, read/write, write-one-to-clear, and many more.

  • Automatic driver generation for register read/write.

  • Data stream for efficient read/write operations with large amounts of data.

  • Read and write function to access AXI IP cores.

  • Automatic tool handling. Easy flow from HDL to a valid bitstream.

  • Bitstream flashing over Ethernet.

  • Testbench generation and compilation of simulation libraries.

  • AXI Access over Python API.

  • Debug monitoring over UART.