Command-Line Interface
XiBIF – Xilinx Board Interface
usage: xibif [-h] [-v] [-p PROJECT]
[--verbosity {debug,info,warning,error,none}]
{new,build,flash,register,simulation,testbench,shell,report,upgrade,settings}
...
Named Arguments
- -v, --version
show program’s version number and exit
- -p, --project
Specify the XiBIF project file to use
- --verbosity
Possible choices: debug, info, warning, error, none
Set the verbosity of the console output
Default:
'info'
subcommands
- command
Possible choices: new, build, flash, register, simulation, testbench, shell, report, upgrade, settings
Sub-commands
new
Create a new XiBIF project
xibif new [-h] [-n NAME] -p PATH [-f | --nuke] -b
{zyboz10,zyboz20,zedboard,zcu104,zcu102,kv260} -x XILINX -v VERSION
Named Arguments
- -n, --name
Name of the project. This name will be used for the tooling project files
Default:
'xibif'
- -p, --path
The path to the directory in which to create the project
- -f, --force
Overwrite an existing XiBIF project (less destructive than –nuke)
Default:
False
- --nuke
Completly remove an existing XiBIF project (more destructive than –force)
Default:
False
- -b, --board
Possible choices: zyboz10, zyboz20, zedboard, zcu104, zcu102, kv260
Name of the FPGA board for this project
- -x, --xilinx
Path to the Xilinx installation folder
- -v, --version
Xilinx tooling version to use
build
Run all build steps for the XiBIF project
xibif build [-h]
[--vivado {installBoard,synthesize,implement,bitstream,export,reportTiming,all} [{installBoard,synthesize,implement,bitstream,export,reportTiming,all} ...]]
[--vitis {update,build,export,bootfile,all} [{update,build,export,bootfile,all} ...]]
[--nowarn-vitis] [--noreport-vivado]
Named Arguments
- --vivado
Possible choices: installBoard, synthesize, implement, bitstream, export, reportTiming, all
Build the Vivado project with the provided stages
Default:
[]
- --vitis
Possible choices: update, build, export, bootfile, all
Build the Vitis project with the provided stages
Default:
[]
- --nowarn-vitis
Disable the warnings about Vitis Bugs
Default:
False
- --noreport-vivado
Do not generate output reports for Vivado
Default:
False
flash
Flash the FPGA with the generated bitstream
xibif flash [-h] [-hw HARDWARE_SERVER] [-p PORT] [-s]
Named Arguments
- -hw, --hardware-server
Hostname or IP address of the computer running hardware server
Default:
'localhost'
- -p, --port
Port of the hardware server
Default:
'3121'
- -s, --start
Start the hardware server on this computer
Default:
False
register
Update the XiBIF Registers from the register file
xibif register [-h] [-s] [-u]
Named Arguments
- -s, --stream
Generate the XiBIF Stream Registers
Default:
False
- -u, --user
Generate the XiBIF User Registers
Default:
False
simulation
Simulate all VHDL testbenches
xibif simulation [-h] [-cx | -cv | -vv {1993,2008} | -l | -t TEST] [-g]
Named Arguments
- -cx, --compilexilinx
Compiles the xilinx library
Default:
False
- -cv, --compilevunit
Compiles the vunit library
Default:
False
- -vv, --vunitvivado
Possible choices: 1993, 2008
Add the vunit library to the Vivado project. The VHDL Version needs to be specified
- -l, --list
List all available testbenches and testcases
Default:
False
- -t, --test
Run only the specified testbench and testcase
- -g, --gui
Open the GUI for the simulation (only valid with -t)
Default:
False
testbench
Generate a testbench from a VHDL file
xibif testbench [-h] -f FILE [-c CLOCK] [-rn RESET_NEGATIVE]
[-rp RESET_POSITIVE] [-e]
Named Arguments
- -f, --file
Name of the VHDL file to generate a testbench for
- -c, --clock
Name of the clock (Multiple clocks can be provided)
- -rn, --reset-negative
Mark the following resets as negative
- -rp, --reset-positive
Mark the following resets as positive
- -e, --type-excel
Generate an accompanying Excel File
Default:
False
shell
Open an interative shell to communicate with a XiBIF board
xibif shell [-h] [--no-connect] [--no-load] [--ip IP]
Named Arguments
- --no-connect
Do not automatially try to connect to the default XiBIF IP address
Default:
False
- --no-load
Do not automatially try to load the default register file
Default:
False
- --ip
The IP address of the board to connect
report
Report an issue to XiBIF’s GitLab page
xibif report [-h] [-l]
Named Arguments
- -l, --log
Open the latest log file
Default:
False
upgrade
Upgrade the VHDL and C source-files to the newest XiBIF version
xibif upgrade [-h]
settings
Change the settings of the XiBIF project
xibif settings [-h] [--project_name PROJECT_NAME]
[--binaries.xilinx_version BINARIES.XILINX_VERSION]
[--binaries.xilinx_path BINARIES.XILINX_PATH]
[--hw.self HW.SELF] [--hw.board HW.BOARD]
[--hw.hdl_src_folder HW.HDL_SRC_FOLDER]
[--hw.hdl_tb_folder HW.HDL_TB_FOLDER]
[--hw.reg_folder HW.REG_FOLDER]
[--hw.sigasi_folder HW.SIGASI_FOLDER]
[--hw.vivado_folder HW.VIVADO_FOLDER]
[--hw.vitis_folder HW.VITIS_FOLDER]
[--results_folder.self RESULTS_FOLDER.SELF]
[--results_folder.compile_xilinx_folder RESULTS_FOLDER.COMPILE_XILINX_FOLDER]
[--results_folder.compile_vunit_folder RESULTS_FOLDER.COMPILE_VUNIT_FOLDER]
[--results_folder.simulation_coverage_folder RESULTS_FOLDER.SIMULATION_COVERAGE_FOLDER]
[--results_folder.simulation_xml_file RESULTS_FOLDER.SIMULATION_XML_FILE]
[--results_folder.simulation_history_folder RESULTS_FOLDER.SIMULATION_HISTORY_FOLDER]
[--sw.self SW.SELF] [--sw.python_folder SW.PYTHON_FOLDER]
[--sw.matlab_folder SW.MATLAB_FOLDER]
[--ethernet.mac ETHERNET.MAC]
[--ethernet.default_ip ETHERNET.DEFAULT_IP]
[--ethernet.default_netmask ETHERNET.DEFAULT_NETMASK]
[--ethernet.default_gateway ETHERNET.DEFAULT_GATEWAY]
[--ethernet.timeout_dhcp_s ETHERNET.TIMEOUT_DHCP_S]
[--ethernet.timeout_connection_drop_ms ETHERNET.TIMEOUT_CONNECTION_DROP_MS]
[--ethernet.connection_drop_flush_fifo {True,False}]
[--doc.self DOC.SELF]
Named Arguments
- --project_name
Name of the project (type: str, default: xibif)
- --binaries.xilinx_version
Version of the Xilinx tools (type: str, default: None)
- --binaries.xilinx_path
Path to the Xilinx tools (type: str, default: None)
- --hw.self
Folder for hardware files (type: str, default: hw)
- --hw.board
Board (type: str, default: None)
- --hw.hdl_src_folder
Folder for HDL source files (type: str, default: src)
- --hw.hdl_tb_folder
Folder for HDL testbench files (type: str, default: tb)
- --hw.reg_folder
Folder for register files (type: str, default: regs)
- --hw.sigasi_folder
Folder for Sigasi project files (type: str, default: ..)
- --hw.vivado_folder
Folder for Vivado project files (type: str, default: vivado)
- --hw.vitis_folder
Folder for Vitis project files (type: str, default: vitis)
- --results_folder.self
Folder for result files (type: str, default: results)
- --results_folder.compile_xilinx_folder
Folder for Xilinx simulation library (type: str, default: compile_xilinx)
- --results_folder.compile_vunit_folder
Folder for VUnit simulation library (type: str, default: compile_vunit)
- --results_folder.simulation_coverage_folder
Folder for simulation coverage files (type: str, default: coverage)
- --results_folder.simulation_xml_file
XML file summarizing simulation results (type: str, default: test_output.xml)
- --results_folder.simulation_history_folder
Folder for VUNIT simulation history files (type: str, default: test_history)
- --sw.self
Folder for software files (type: str, default: sw)
- --sw.python_folder
Folder for Python files (type: str, default: python)
- --sw.matlab_folder
Folder for MATLAB files (type: str, default: matlab)
- --ethernet.mac
MAC address (type: str, default: 00:0a:35:d0:22:dc)
- --ethernet.default_ip
Default IP address (type: str, default: 192.168.1.10)
- --ethernet.default_netmask
Default network mask (type: str, default: 255.255.255.0)
- --ethernet.default_gateway
Default gateway (type: str, default: 192.168.1.1)
- --ethernet.timeout_dhcp_s
DHCP timeout in seconds (type: int, default: 10)
- --ethernet.timeout_connection_drop_ms
Connection drop timeout in milliseconds (type: int, default: 1000)
- --ethernet.connection_drop_flush_fifo
Possible choices: True, False
Flag to flush FIFO on connection drop (type: bool, default: False)
- --doc.self
Folder for documentation files (type: str, default: doc)