Troubleshooting Guide

This section is dedicated to common road bumps or problems while using XiBIF.

Project Building

Invalid Path to Xilinx Executable

It may occur that a non-existing path to a Xilinx executable is given/entered into the .xibif file. Naturally, the executables are not found and the program terminates.

Linker Script Path

When a version of XiBIF prior to 4.1 is used to create a project, the linker script path in Vitis is not given relative to the project but as an absolute path. When a project is moved, this path does not change and thus the linker script cannot be found.

Vitis cannot find fsbl.elf

Aaaah, Vitis is a really well written piece of software, isn’t it? Failure to find an fsbl.elf file (the bootloader) usually comes from parts of the project having a path that is too long. Vitis generates deeply nested directories, so even if you are only a few folders deep, it may fail.

The easiest fix for this issue is to move the project further upwards in the directory tree.

Connection Issues

USB-to-Ethernet Bug

The Windows driver for some USB-to-Ethernet adapters seems to have a bug when used on a USB 3.x port. If you experience an unstable connection, try a USB 2.0 port.

Enabling I- and D-Cache

Sometimes it can occur that an application using the streaming feature crashes for no apparent reason. We suspect this is a software bug on Vitis side. It can sometimes be fixed by uncommenting the Disable I- and D-cache statements in the main.c file.

Firewall

XiBIF communicates over the network port 6 & 7. Additionally, the hardware server from Xilinx requires the port 3121 to be open.

Ensure that your firewall allows communication over these ports.

No Response from FPGA

  • Check the IP Settings: Ensure the computer and XiBIF board have the correct IP addresses.

  • Network Adapter: Ensure the Ethernet adapter is enabled and properly connected.

  • Firewall Issues: Temporarily turn off any firewalls or security software that might block the connection.

  • WSL: If you are using Windows Subsystem for Linux, the network interfaces to your computer are unreachable from Linux by default. You must manually add the network route to your computer’s routing table.

Streaming Issues

No AXI Stream Data

Consider the following questions when you are unable to receive data over the stream interface.

  • Is the Stream source actually producing data?

  • Are the AXI-Stream signals set correctly? Can you prove it in a simulation?

  • Are there other AXI-Stream sources that might block your data from arriving?

  • Is the design that you are simulating actually loaded onto the FPGA?

Installation

Cannot update beyond 4.1.0

Most of the time when updating via PIP does not work as expected, it is due to a missing dependency. For v4.1.0 specifically, we added support for a custom tool for testbench generation called hdltbgen. When this tool is missing, installing a newer version is not possible.

Use pip install hdltbgen --index-url https://gitlab.ost.ch/api/v4/projects/10916/packages/pypi/simple to install the tool.